Aldec Supports Xilinx Virtex-II Pro Devices with Mixed HDL Simulation Technology

Henderson Nevada, September 9, 2002 -- Aldec, Inc., a pioneer in mixed language simulation and advanced design tools for FPGA and ASIC devices, today announced complete device support for Xilinx® new Virtex-II Pro™ devices. Using Aldec’s mixed language simulation technology, support for Rocket I/O transceivers and PowerPC processors on a single chip is completely streamlined. Aldec’s verification tools fully support these high-capacity chips in the FPGA market and not only accelerate time-to-market, but offer industry-leading flexibility and premium cost efficacy.

Aldec offers the most comprehensive FPGA support for Xilinx’s latest Virtex-II and Virtex-II Pro devices at the lowest price point on the market. The combination of speed, flexibility and device density makes the latest release of the Virtex-II Pro devices invaluable to FPGA designers with complex designs.

“Device support of Aldec’s product line is unparalleled,” stated Megan Moran, Product Marketing Manager of Active-HDL. “Many other verification tools that support Rocket I/O transceivers and PowerPC hard cores come at a much higher price point, which makes it a prohibitive solution for most FPGA designers. Aldec’s tools contain the SmartModel support necessary for Xilinx high-density devices and extend its support for embedded components as well.”

Aldec’s unique support for Virtex-II Pro devices comes from its SWIFT™ Model Support Interface. By including the SmartModel Library™ in its simulation technology, Aldec’s verification tools can automatically initialize the model in order to support the PowerPC component within its mixed simulation kernel. Aldec’s tools include precompiled wrappers for PowerPC and I/O components (PPC405 and GT design units) referring to the SmartModel Library. The SWIFT model of the PowerPC can execute the processor code, enabling complete software verification along with the hardware.

Aldec’s inclusion of SmartModel support provides the functional equivalency of all Virtex-II Pro hardware modules. Simulation results for both the hardware and software may then be viewed in Aldec’s Waveform Viewer and may even be graphically edited and back-annotated into the original code. Simulation with SWIFT models is very accurate and includes all of the timing information regarding the actual device. The designer can verify the bus behavior with timing accuracy.

The SmartModel interface is an API developed by Synopsys® that allows behavioral models from the SmartModels Library to be directly imported within Aldec’s verification tools. Ordinarily, Virtex-II Pro devices cannot be simulated at the gate level because of the inclusion of embedded processors, so Aldec customers can instead use SmartModels representing integrated circuits and system buses as “black boxes” that accept input stimulus and respond with appropriate output behavior. Additionally, such behavioral models provide improved performance over gate-level models.

Aldec’s tools allow the use of the SmartModels Library in VHDL, Verilog and mixed language designs and interface to this library through either a foreign architecture or the PLI routines. The user can observe the internal registers of the CPU during the simulation and accurately debug any software problems discovered during the simulation.

Virtex-II Pro devices contain a foreign attribute string that associates a specific Smart Model with the PowerPC. During initialization of the simulation, the Smart Model Library interface is loaded automatically and the communication with PowerPC is established.

“Aldec verification tools continue to be on the cutting-edge in regards to support for the highest-density devices, as support for the new Virtex-II Pro devices through SmartModels illustrates. That, in combination with our low price points, ensure that all FPGA designers have access to the most complete silicon solutions available,” stated Megan Moran.

Availability
All of Aldec’s products support any combination of synthesis and implementation tools, including the latest Virtex-II Pro support. Both Aldec’s Active-HDL and Riviera products support the latest Virtex-II Pro architecture with SWIFT SmartModel support. To receive your FREE evaluation copy of Active-HDL or Riviera, contact Aldec at www.aldec.com.

About Aldec
Aldec, Inc., an 18-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers’ needs. It is recognized that to be productive in today’s market and to best serve customers in the future, new technologies and innovations that go beyond traditional methods of conducting business in the EDA industry must be pursued. Aldec is committed to customer service and is actively developing a company that will evolve along with its customers’ designs. Additional information about Aldec is available at http://www.aldec.com.



Active-HDL is a trademark of Aldec, Inc. Virtex-II Pro is a trademark of Xilinx, Inc. SWIFT and SmartModel Library are trademarks of Synopsys. All other trademarks or registered trademarks are property of their respective owners

Contact:        Megan Moran        
Aldec, Inc.
(702) 990-4400 ext. 201        
meganm@aldec.com